As those skilled in the pertinent art understand, packaged integrated circuits (ICs) tend to produce electromagnetic interference (EMI), which can impair radio-frequency (RF) communication or the operation of neighboring circuits/systems. One way to reduce EMI is to operate EMI-producing circuits not at a fixed clock frequency, but at a frequency that varies over time. This spreads the energy of EMI over a band of frequencies and reduces the interference observed over any given single frequency.
A circuit configured to produce a clock with frequency that varies over time is referred to as a spread-spectrum (SS) clock generator (SSCG). In a typical embodiment, a SSCG will ramp the frequency of the clock signal in a periodic, saw-tooth pattern, with the range and periodicity governed by the application's specification. A typical modulation range is on the order of a few thousand parts per million (ppm), with 5000 ppm being a common value. A typical modulation rate is on the order of tens of kilohertz (kHz), with 33 kHz being a common value. The modulation is typically “down-spread”, which means the clock frequency is only modulated downward from a nominal frequency, and modulated back up to the nominal frequency from a minimum frequency value.
A fundamental circuit implementation of a SSCG is a phase-locked loop (PLL). Although analog PLLs have historically been used in SSCGs, analog PLL designs require significant labor to migrate from one IC process technology to another. In contrast, digital PLLs have been demonstrated to be far more portable.
A PLL commonly contains a phase-and-frequency detector, which will produce an error signal based on the difference between reference clock and output clock phases. The error signal is then fed into a digital phase and frequency controller. PLLs can be linear or nonlinear. In a linear PLL, the error signal magnitude is proportional to the difference between the two phases, while in a nonlinear PLL, the error signal only indicates the direction of error. While analog PLLs are exclusively linear, digital PLLs can be designed to be linear or nonlinear. However, because linear digital PLLs have been demonstrated to be costly in complexity and power consumption, nonlinear varieties are heavily preferred. A bang-bang digital PLL (BBDPLL) is a common implementation of a nonlinear digital PLL.